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copyright ? cirrus logic, inc. 2007 (all rights reserved) http://www.cirrus.com 114 db, 192 khz 6 -channel d/a converter features ? advanced multi-bit delta sigma architecture ? 24-bit conversion ? automatic detection of sample rates up to 192 khz ? 114 db dynamic range ? -100 db thd+n ? direct stream digital mode ? non-decimating volume control ? on-chip 50 khz filter ? matched pcm and dsd analog output levels ? selectable digital filters ? volume control with 1/2-db step size and soft ramp ? low clock jitter sensitivity ? +5 v analog supply, +2.5 v digital supply ? separate 1.8 to 5 v logic supplies for the control & serial ports description the cs4365 is a complete 6- channel digital-to-analog system. this d/a system includes digital de-emphasis, half-db step size volume control, atapi channel mix- ing, selectable fast and slow digital interpolation filters followed by an oversampled, multi-bit delta sigma mod- ulator which includes mi smatch-shaping technology that eliminates distortion due to capacitor mismatch. following this stage is a mu lti-element switched capac- itor stage and low-pass filt er with differential analog outputs. the cs4365 also has a proprietary dsd processor which allows for vo lume control and 50 khz on-chip fil- tering without an intermediate decimation stage. it also offers an optional path for direct dsd conversion by di- rectly using the multi-element switched capacitor array. the cs4365 is available in a 48-pin lqfp package in both commercial (-40 to +85) and automotive (-40 to +105) grades. the cdb4365 customer dem- onstration board is also available for device evaluation and implementation suggestions. please see ?ordering information? on page 51 for complete details. the cs4365 accepts pcm data at sample rates from 4 khz to 216 khz, dsd audio data, and delivers excel- lent sound quality. these features are ideal for multi- channel audio systems, including sacd players, a/v receivers, digital tv?s, mixing consoles, effects proces- sors, sound cards, and automotive audio systems. control port supply = 1.8 v to 5 v register/hardware configuration internal voltage reference reset s e ria l inte rfa ce level translator level translator tdm serial audio input digital supply = 2.5 v hardware mode or i 2 c/spi software mode control data analog supply = 5 v six channels of differential outputs 6 6 pcm serial audio input volume controls digital f ilters switch-cap dac and analog filters multi-bit ? modulators dsd audio input dsd processor -volume control -50 khz filter e xternal mute control mute signals 6 6 serial audio port supply = 1.8 v to 5 v april '07 ds670f1 cs4365
2 ds670f1 cs4365 table of contents 1. pin description ........................................................................................................... ..................... 6 2. characteristics and specificat ions .......... ................. ................ ................ ................ ........... 8 recommended operating conditions ..................................................................................... 8 absolute maximum rating s ................ ................. ................ ................ ............. ............. ........... ... 8 power and thermal characteristics .................................................................................. 11 3. typical connection diagram ................................................................................................ .. 19 4. applications ............................................................................................................... .................... 21 4.1 master clock .............................................................................................................. ..................... 21 4.2 mode select ............................................................................................................... ..................... 22 4.3 digital interface formats ................................................................................................. ............... 23 4.3.1 olm #1 .................................................................................................................. ................ 24 4.3.2 olm #2 .................................................................................................................. ................ 24 4.4 oversampling modes ........................................................................................................ .............. 24 4.5 interpolation filter ...................................................................................................... ..................... 25 4.6 de-emphasis ............................................................................................................... ................... 25 4.7 atapi specification ....................................................................................................... ................. 26 4.8 direct stream digital (dsd) mode .......................................................................................... ........ 26 4.9 grounding and power su pply arrangements ................................................................................. 27 4.9.1 capacitor placement ...... ............................................................................................... ........ 27 4.10 analog output and filtering .............................................................................................. ............ 28 4.11 the mutec outputs ........................................................................................................ ............ 29 4.12 recommended power-up sequence ........................................................................................... 2 9 4.12.1 hardware mode .......................................................................................................... ......... 29 4.12.2 software mode .......................................................................................................... .......... 30 4.13 recommended procedure for sw itching operational modes ....................................................... 30 4.14 control port interface ... ................................................................................................ ................ 30 4.14.1 map auto increment .... ................................................................................................. ...... 30 4.14.2 i2c mode ............................................................................................................... ............... 30 4.14.2.1 i2c write? ........................................................................................................... .... 31 4.14.2.2 i2c read ............................................................................................................. ..... 31 4.14.3 spi? mode .............................................................................................................. ........... 32 4.14.3.1 spi write ............................................................................................................ ...... 32 4.15 memory address pointer (m ap) ....................................................................................... ...... 32 4.15.1 incr (auto map increment enable) .................................................................................... 32 4.15.2 map4-0 (mem ory address pointer) .................................................................................... 32 5. register quick reference .................................................................................................. ..... 33 6. register description ....................................................................................................... ........... 34 6.1 chip revision (address 01h) .............................................................................................. ........... 34 6.1.1 part number id (part) [read only] .................................................................................... 34 6.2 mode control 1 (address 02h) ................. ............................................................................. .......... 34 6.2.1 control port enable (cpen) .............................................................................................. .... 34 6.2.2 freeze controls (freeze) ................................................................................................ ... 34 6.2.3 pcm/dsd selection (dsd/pcm) .......................................................................................... 35 6.2.4 dac pair disable (dacx_dis) ............................................................................................. .35 6.2.5 power down (pdn) ........................................................................................................ ....... 35 6.3 pcm control (address 03h) ................................................................................................ ........... 35 6.3.1 digital interface format (dif) .......................................................................................... ...... 35 6.3.2 functional mode (fm) ........................... ......................................................................... ....... 36 6.4 dsd control (address 04h) ................................................................................................ ........... 36 6.4.1 dsd mode digital interface format (dsd_dif) .................................................................... 36 6.4.2 direct dsd conversion (dir_dsd) ...................................................................................... 37 6.4.3 static dsd detect (static_dsd) ........................................................................................ 37
ds670f1 3 cs4365 6.4.4 invalid dsd detect (invalid_dsd) ........... .......................................................................... 37 6.4.5 dsd phase modulation mode select (dsd_pm_mode) ..................................................... 37 6.4.6 dsd phase modulation mode enable (dsd_pm_en) ......................................................... 37 6.5 filter control (address 05h) ............................................................................................. .............. 38 6.5.1 interpolation filter select (filt_sel) .................................................................................. .38 6.6 invert control (address 06h) ................... .......................................................................... ............. 38 6.6.1 invert signal polarity (inv_xx) ............. ............................................................................ ....... 38 6.7 group control (address 07h) .............................................................................................. ........... 38 6.7.1 mute pin control (mutec1, mutec0) ................................................................................. 38 6.7.2 channel a volume = channel b volume (px_a=b) .............................................................. 39 6.7.3 single volume control (snglvol) ............ .......................................................................... 39 6.8 ramp and mute (address 08h) .............................................................................................. ........ 39 6.8.1 soft ramp and zero cross control (szc) ...................................................................... 39 6.8.2 soft volume ramp-up after error (rmp_up) ....................................................................... 40 6.8.3 soft ramp-down befo re filter mode change (rmp_dn) ..................................................... 40 6.8.4 pcm auto-mute (pamute) .................................................................................................. 40 6.8.5 dsd auto-mute (damute) .................................................................................................. .41 6.8.6 mute polarity and detect (mutep1:0) ............................................................................ 41 6.9 mute control (address 09h) ............................................................................................... ............ 41 6.9.1 mute (mute_xx) ................................... ....................................................................... ......... 41 6.10 mixing control (address 0ah, 0dh, 10h, 13 h) ............................................................................. 42 6.10.1 de-emphasis control (px_de m1:0) ................................................................................... 42 6.11 atapi channel mixing and muting (atapi) ................................................................................. 4 2 6.12 volume control (address 0bh, 0ch, 0eh, 0fh, 11h, 12h) ........................................................... 43 6.12.1 digital volume control ( xx_vol7:0) ................................................................................... 43 6.13 pcm clock mode (address 16h) ............................................................................................ ..... 44 6.13.1 master clock divide by 2 enable (mclkdi v) ................................................................ 44 7. filter plots ............................................................................................................... ...................... 45 8. parameter definitions ...................................................................................................... .......... 49 9. package dimensions ........................................................................................................ ........... 50 10. ordering information ...................................................................................................... ........ 51 11. references ................................................................................................................ .................... 51 12. revision history ......................................................................................................... ................ 52
4 ds670f1 cs4365 list of figures figure 1.serial audio interface timing ........................................................................................ .............. 15 figure 2.direct stream digital - se rial audio input timing .................................................................... .... 16 figure 3.direct stream digital - seri al audio input timing for phase mo dulation mode ........................... 16 figure 4.control port timing - i2c format ..................................................................................... ............ 17 figure 5.control port timing - spi format ..................................................................................... ........... 18 figure 6.typical connection diagram, software mo de ............................................................................ .19 figure 7.typical connection diagram, hardware mode ........................................................................... 2 0 figure 8.format 0 - left-justified up to 24-bit data .......................................................................... ........ 23 figure 9.format 1 - i2s up to 24-bit data ..... ................................................................................ ............. 23 figure 10.format 2 - right-justified 16-bit data .............................................................................. ......... 23 figure 11.format 3 - right-justified 24-bit data .............................................................................. ......... 23 figure 12.format 4 - right-justified 20-bit data .............................................................................. ......... 23 figure 13.format 5 - right-justified 18-bit data .............................................................................. ......... 24 figure 14.format 8 - one-line mode 1 .............. ............................................................................ ........... 24 figure 15.format 9 - one-line mode 2 .............. ............................................................................ ........... 24 figure 16.de-emphasis curve ................................................................................................... ............... 25 figure 17.atapi block diagram (x = channel pair 1, 2, or 3) ................................................................... 26 figure 18.dsd phase modulation mode diagram ................................................................................... .27 figure 19.full-scale output ................................................................................................... ................... 28 figure 20.recommended output filter ........................................................................................... .......... 28 figure 21.recommended mute circuitry .......................................................................................... ........ 29 figure 22.control port timing, i2c mode ....................................................................................... ........... 31 figure 23.control port timing, spi mode .......... ............................................................................. .......... 32 figure 24.single-speed (fast) stopband rejection .............................................................................. ..... 45 figure 25.single-sp eed (fast) transition band ................... .............................................................. ........ 45 figure 26.single-speed (fast) transition band (detail) .......... .............................................................. ..... 45 figure 27.single-sp eed (fast) passband ripple ................. ................................................................ ...... 45 figure 28.single-sp eed (slow) stopband rejection .............................................................................. ... 45 figure 29.single-speed (slow) transition band ................................................................................. ....... 45 figure 30.single-speed (slow) transition band (detail) ........................................................................ .... 46 figure 31.single-sp eed (slow) passband ripple ...................... ........................................................... ..... 46 figure 32.double-speed (fast) stopband rejection .............................................................................. ... 46 figure 33.double-speed (fast) transition band ................................................................................. ....... 46 figure 34.double-spee d (fast) transition band (detail) ........................................................................ .... 46 figure 35.double-speed (fast) pa ssband ripple ................................................................................. ..... 46 figure 36.double-speed (slo w) stopband rejection .............................................................................. .. 47 figure 37.double-speed (slo w) transition band ................................................................................. ..... 47 figure 38.double-speed (slo w) transition band (detail) ............. ........................................................... .. 47 figure 39.double-speed (slo w) passband ripple ................................................................................. ... 47 figure 40.quad-speed (fast) stopband rejection ................................................................................ .... 47 figure 41.quad-speed (fast) transition band ................................................................................... ....... 47 figure 42.quad-speed (fast) transition band (detail) .......................................................................... .... 48 figure 43.quad-speed (fast) passb and ripple ................................................................................... ..... 48 figure 44.quad-speed (slow) stopband rejection ................................................................................ ... 48 figure 45.quad-speed (slow) transition band ...... ............................................................................. ...... 48 figure 46.quad-speed (slow) tran sition band (detail) .......................................................................... ... 48 figure 47.quad-speed (slow) passband ripple ................................................................................... .... 48
ds670f1 5 cs4365 list of tables table 1. single-speed mode standa rd frequencies ............................................................................... .21 table 2. double-speed mode standard frequencies ............................................................................... 21 table 3. quad-speed mode standard frequencies ................................................................................. 21 table 4. pcm digital interface format, hardware mo de options ............................................................. 22 table 5. mode selection, hardware mode options ................................................................................ .. 22 table 6. direct stream digital (dsd ), hardware mode options ............ ................................................... 22 table 7. digital interface formats - pcm mode . ................................................................................ ....... 36 table 8. digital interface format s - dsd mode ................................................................................. ....... 36 table 9. atapi decode table ................................................................................................... ............... 42 table 10. example digital volume settings ....... .............................................................................. ......... 43
6 ds670f1 cs4365 1. pin description pin name # pin description vd 4 digital power ( input ) - positive power supply for the digital section. refer to the recom- mended operating conditions for appropriate voltages. gnd 5, 31 ground ( input ) - ground reference. should be connected to analog ground. mclk 6 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. tables 1 through 3 illustrate several standard audio sample rates and the required master clock fre- quencies. lrck 7 left right clock ( input ) - determines which channel, left or right, is currently active on the serial audio data line. the frequency of the left/r ight clock must be at the audio sample rate, fs. sdin1 sdin2 sdin3 8 11 13 serial data input ( input ) - input for two?s complement serial audio data. sclk 9 serial clock ( input ) - serial clocks for the serial audio interface. tst 14 44 45 test - these pins need to be tied to analog ground. rst 19 reset ( input ) - the device enters a low power mode and all internal registers are reset to their default settings when low. va 32 analog power ( input ) - positive power supply for the analog section. refer to the recom- mended operating conditions for appropriate voltages. vls 43 serial audio interface power ( input ) - determines the required signal level for the serial audio interface. refer to the recommended oper ating conditions for appropriate voltages. vlc 18 control port power ( input ) - determines the required signal le vel for the control port and hardware mode configuration pins. refer to the recommended operating conditions for appropriate voltages. sdin3 gnd aoutb2- aouta3+ aoutb3- aoutb2+ va aouta3- aoutb3+ mutec2 mutec3 6 2 4 8 10 1 3 5 7 9 11 1 2 13 14 15 16 17 18 19 20 21 22 23 24 31 35 33 29 27 36 34 32 30 28 26 25 48 47 46 45 44 43 42 41 40 39 38 37 mclk dsdb1 vd sdin1 m4(tst) dsda2 dsda1 gnd sclk sdin2 m3(tst) lrck dsd_sclk dsdb3 dsda3 tst cs4365 tst vls tst m2(scl/cclk) m1(sda/cdin) vlc rst filt+ vq mutec6 mutec5 mutec4 m0(ad0/cs) aouta2+ aouta2- aoutb1+ aoutb1- aouta1- aouta1+ dsdb2 mutec1
ds670f1 7 cs4365 vq 21 quiescent voltage ( output ) - filter connection for internal quiescent voltage. vq must be capacitively coupled to analog ground, as shown in the typical connection diagram. the nom- inal voltage level is specified in the analog char acteristics and specifications section. vq pre- sents an appreciable source impedance and any current drawn from this pin will alter device performance. however, vq can be used to bias the analog circuitry assuming there is no ac signal component and the dc current is less t hen the maximum specified in the analog char- acteristics and specifications section. filt+ 20 positive voltage reference ( output ) - positive reference voltage for the internal sampling cir- cuits. requires the capacitive decoupling to analog ground as shown in the typical connection diagram. aouta1 +,- aoutb1 +,- aouta2 +,- aoutb2 +,- aouta3 +,- aoutb3 +,- 39,40 37,38 35,36 33,34 29,30 27,28 differential analog output ( output ) - the full-scale differential analog output level is specified in the analog characteristics specification table. mutec1 mutec2 mutec3 mutec4 mutec5 mutec6 41 26 25 24 23 22 mute control ( output ) - the mute control pins go high during power-up initialization, reset, muting, power-down or if the master clock to le ft/right clock frequency ratio is incorrect. these pins are intended to be used as a control for external mute circuits on the line outputs to pre- vent the clicks and pops that can occur in any si ngle supply system. use of mute control is not mandatory but recommended for designs requirin g the absolute minimum in extraneous clicks and pops. hardware mode definitions m0 m1 m2 m3 m4 17 16 15 12 10 mode selection ( input ) - determines the operational mode of the device as detailed in table 6 and table 7 . software mode definitions scl/cclk 15 serial control port clock ( input ) - serial clock for the serial control port. requires an external pull-up resistor to the logic interface voltage in i2c mode as shown in the typical connection diagram. sda/cdin 16 serial control port data ( input/output ) - sda is a data i/o line in i2c mode and is open drain, requiring an external pull-up resistor to the logic interface voltage, as shown in the typical con- nection diagram; cdin is the input data line for the control port interface in spi mode. ad0/cs 17 address bit 0 (i2c) / contro l port chip select (spi) ( input ) - ad0 is a chip address pin in i2c mode; cs is the chip-select signal for spi mode. tst 10, 12 test - these pins need to be tied to analog ground. dsd definitions dsda1 dsdb1 dsda2 dsdb2 dsda3 dsdb3 3 2 1 48 47 46 direct stream digital input ( input) - input for direct stream digital serial audio data. gnd if unused. dsd_sclk 42 dsd serial clock (input) - serial clock for the di rect stream digital serial audio interface. pin name # pin description
8 ds670f1 cs4365 2. characteristics and specifications recommended operating conditions gnd = 0 v; all voltages with respect to ground. absolute maximum ratings gnd = 0 v; all voltages with respect to ground. warning: operation at or beyond these limit s may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameters symbol min typ max units dc power supply analog power digital internal power serial data port interface power control port interface power va vd vls vlc 4.75 2.37 1.71 1.71 5.0 2.5 5.0 5.0 5.25 2.63 5.25 5.25 v v v v ambient operating temperature (power applied) commercial grade (-cqz) automotive grade (-dqz) t a -40 -40 - - + 85 +105 c c parameters symbol min max units dc power supply analog power digital internal power serial data port interface power control port interface power va vd vls vlc -0.3 -0.3 -0.3 -0.3 6.0 3.2 6.0 6.0 v v v v input current any pin except supplies i in -10ma digital input voltage serial data port interface control port interface v ind-s v ind-c -0.3 -0.3 vls+ 0.4 vlc+ 0.4 v v ambient operating temperature (power applied) t op -55 125 c storage temperature t stg -65 150 c
ds670f1 9 cs4365 dac analog characteristi cs - commercial (-cqz) test conditions (unless otherwise specified): va = vls = vlc = 5 v; vd = 2.5 v; t a = 25c; full-scale 997 hz input sine wave (note 1) ; tested under max ac-load resistance ; valid with filt+ and vq capacitors as shown in ?typical connection diagram? on page 19 ; measurement bandwidth 10 hz to 20 khz. notes: 1. one-half lsb of triangular pdf dither is added to data. 2. performance limited by 16-bit quantization noise. 3. v fs is tested under load r l and includes attenuation due to z out . parameters symbol min typ max unit fs = 48 khz, 96 khz, 192 khz and dsd dynamic range 24-bit a-weighted unweighted 16-bit a-weighted (note 2) unweighted 108 105 - - 114 111 97 94 - - - - db db db db total harmonic distortion + noise 24-bit 0 db -20 db -60 db (note 2) 16-bit 0 db -20 db -60 db thd+n - - - - - - -100 -91 -51 -94 -74 -34 -94 - -45 - - - db db db db db db idle channel noise / signal-to-noise ratio a-weighted - 114 - db interchannel isolation (1 khz) - 110 - db dc accuracy interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/ c analog output full-scale differential- pcm, dsd processor output voltage (note 3) direct dsd mode v fs 1.28?v a 0.90?v a 1.32?v a 0.94?v a 1.36?v a 0.98?v a vpp vpp output impedance z out - 130 - max dc current draw from an aout pin i outmax -1.0-ma min ac-load resistance r l -3-k max load capacitance c l - 100 - pf quiescent voltage vq - 50% v a -vdc max current draw from vq i qmax -10- a
10 ds670f1 cs4365 dac analog characteristic s - automotive (-dqz) test conditions (unless otherwise spec ified): va = 4.75 to 5.25 v; vls = 1.71 to 5.25 v; vlc = 1.71 to 5.25 v; vd = 2.37 to 2.63 v; t a = -40c to 85c; full-scale 997 hz input sine wave (note 1) ; tested under max ac-load resistance ; valid with filt+ and vq capacitors as shown in ?typical connection diagram? on page 19 ; measure- ment bandwidth 10 hz to 20 khz. parameters symbol min typ max units fs = 48 khz, 96 khz, 192 khz and dsd dynamic range (note 1) 24-bit a-weighted unweighted 16-bit a-weighted (note 2) unweighted 105 102 - - 114 111 97 94 - - - - db db db db total harmonic distortion + noise (note 1) 24-bit 0 db -20 db -60 db (note 2) 16-bit 0 db -20 db -60 db thd+n - - - - - - -100 -91 -51 -94 -74 -34 -91 - -42 - - - db db db db db db idle channel noise / signal-to-noise ratio a-weighted - 114 - db interchannel isolation (1 khz) - 110 - db dc accuracy interchannel gain mismatch - 0.1 - db gain drift - 100 - ppm/c analog output full-scale differential- pcm, dsd processor output voltage (note 3) direct dsd mode v fs 1.28?v a 0.90?v a 1.32?v a 0.94?v a 1.36?v a 0.98?v a vpp vpp output impedance z out -130 - max dc current draw from an aout pin i outmax -1.0 -ma min ac-load resistance r l -3 -k max load capacitance c l -100 -pf quiescent voltage vq - 50% v a -vdc max current draw from vq i qmax -10 - a
ds670f1 11 cs4365 power and thermal characteristics notes: 4. current consumption increases with increasing fs within a given speed mode and is signal dependant. max values are based on highest fs and highest mclk. 5. i lc measured with no external loading on the sda pin. 6. power-down mode is defined as rst pin = low with all clock and data lines held static. 7. valid with the recommended capacitor values on filt+ and vq as shown in 6 and 7 . parameters symbol min typ max units power supplies power supply current normal operation, va= 5 v (note 4) vd= 2.5 v (note 5) interface current, vlc=5 v vls=5 v (note 6) power-down state (all supplies) i a i d i lc i ls i pd - - - - - 60 16 2 84 200 65 22 - - - ma ma a a a power dissipation (note 4) va = 5v, vd = 2.5v normal operation (note 6) power-down - - 340 1 390 - mw mw package thermal resistance ja jc - - 48 15 - - c/watt c/watt power supply rejection ratio (note 7) (1 khz) (60 hz) psrr - - 60 40 - - db db
12 ds670f1 cs4365 combined interpolat ion & on-chip analog filter response the filter characteristics have been normalized to the sa mple rate (fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by fs. see note 12 . notes: 8. slow roll-off interpolation filter is only available in software mode. 9. response is clock-dependent and will scale with fs. 10. for single-speed mode, the measurement bandwidth is from stopband to 3 fs. for double-speed mode, the measurement bandwidth is from stopband to 3 fs. for quad-speed mode, the measurement bandwidth is from stopband to 1.34 fs. 11. de-emphasis is available only in single-speed m ode; only 44.1 khz de-emphasis is available in hard- ware mode. 12. amplitude vs. frequency plots of this data are available in section 7. ?filter plots? on page 45 . parameter fast roll-off unit min typ max combined digital and on-chip analog filter response - single-speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 10) 102 - - db group delay - 10.4/fs - s de-emphasis error (note 11) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.36 0.21 0.14 db db db combined digital and on-chip analog filter response - double-speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 10) 80 - - db group delay - 6.15/fs - s combined digital and on-chip analog filter response - quad-speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .635 - - fs stopband attenuation (note 10) 90 - - db group delay - 7.1/fs - s
ds670f1 13 cs4365 combined interpolation & on-c hip analog filter response (continued) dsd combined digital & on-c hip analog filter response parameter slow roll-off (note 8) unit min typ max single-speed mode - 48 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - 0.417 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 10) 64 - - db group delay - 7.8/fs - s de-emphasis error (note 11) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.36 0.21 0.14 db db db double-speed mode - 96 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .296 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .792 - - fs stopband attenuation (note 10) 70 - - db group delay - 5.4/fs - s quad-speed mode - 192 khz passband (note 9) to -0.01 db corner to -3 db corner 0 0 - - .104 .481 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .868 - - fs stopband attenuation (note 10) 75 - - db group delay - 6.6/fs - s parameter min typ max unit dsd processor mode passband (note 9) to -3 db corner 0 - 50 khz frequency response 10 hz to 20 khz -0.05 - +0.05 db roll-off 27 - - db/oct direct dsd mode passband (note 9) to -0.1 db corner to -3 db corner 0 0 - - 26.9 176.4 khz khz frequency response 10 hz to 20 khz -0.1 - 0 db
14 ds670f1 cs4365 digital characteristics notes: 13. any pin except supplies. transie nt currents of up to 100 ma on th e input pins will not cause scr latch- up. parameters symbol min typ max units input leakage current (note 13) i in --10 a input capacitance - 8 - pf high-level input voltage serial i/o control i/o v ih v ih 0.70?v ls 0.70?v lc - - - - v v low-level input voltage serial i/o control i/o v il v il - - - - 0.30?v ls 0.30?v lc v v low-level output voltage (i ol = -1.2 ma) control i/o = 3.3 v, 5 v v ol - - 0.20?v lc v low-level output voltage (i ol = -1.2 ma) control i/o = 1.8 v, 2.5 v v ol - - 0.25?v lc v mutec auto detect input high voltage v ih 0.70?v a --v mutec auto detect input low voltage v il - - 0.30?v a v maximum mutec drive current i max -3-ma mutec high-level output voltage v oh -va-v mutec low-level output voltage v ol -0-v
ds670f1 15 cs4365 switching charact eristics - pcm inputs: logic 0 = gnd, logic 1 = vls, c l = 20 pf. notes: 14. after powering up, rst should be held low until after the power supplies and clocks are settled. 15. see tables 1 - 3 for suggested mclk frequencies. 16. msb of ch1 is always the second sclk rising edge following lrck rising edge. parameters symbol min max units rst pin low pulse width (note 14) 1-ms mclk frequency 1.024 55.2 mhz mclk duty cycle (note 15) 45 55 % input sample rate - lrck (manual selection) single-speed mode double-speed mode quad-speed mode f s f s f s 4 50 100 54 108 216 khz khz khz input sample rate - lrck (auto detect) single-speed mode double-speed mode quad-speed mode fs fs fs 4 84 170 54 108 216 khz khz khz lrck duty cycle 45 55 % sclk duty cycle 45 55 % sclk high time t sckh 8-ns sclk low time t sckl 8-ns lrck edge to sclk rising edge t lcks 5-ns sclk rising edge to lrck falling edge t lckd 5-ns sdin setup time before sclk rising edge t ds 3-ns sdin hold time after sclk rising edge t dh 5-ns sdinx t ds sclk lrck msb t dh t sckh t sckl t lcks msb-1 figure 1. serial audio interface timing
16 ds670f1 cs4365 switching characteristics - dsd logic 0 = gnd; logic 1 = vls; c l =20pf . parameter symbol min typ max unit mclk duty cycle 40 - 60 % dsd_sclk pulse width low t sclkl 160 - - ns dsd_sclk pulse width high t sclkh 160 - - ns dsd_sclk frequency (64x oversampled) (128x oversampled) 1.024 2.048 - - 3.2 6.4 mhz mhz dsd_a / _b valid to dsd_sclk rising setup time t sdlrs 20 - - ns dsd_sclk rising to dsd_a or dsd_b hold time t sdh 20 - - ns dsd clock to data transition (phase modulation mode) t dpm -20 - 20 ns sclkh t sclkl t dsdxx dsd_sclk sdlrs t sdh t figure 2. direct stream digital - serial audio input timing dpm t dsdxx dsd_sclk (64fs) dsd_sclk (128fs) dpm t figure 3. direct stream digital - serial audio input timing for phase modulation mode
ds670f1 17 cs4365 switching characteristics - control port - i2c format inputs: logic 0 = gnd, logic 1 = vlc, c l =20pf. notes: 17. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 17) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 4. control port timing - i2c format
18 ds670f1 cs4365 switching characteristics - control port - spi ? format inputs: logic 0 = gnd, logic 1 = vlc, c l =20pf. notes: 18. t spi is only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 19. data must be held for sufficient time to bridge the transition time of cclk. 20. for f sck < 1 mhz. parameter symbol min max unit cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 18) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 19) t dh 15 - ns rise time of cclk and cdin (note 20) t r2 - 100 ns fall time of cclk and cdin (note 20) t f2 - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 5. control port timing - spi format
ds670f1 19 cs4365 3. typical connec tion diagram vls mclk vd aouta1+ 8 32 0.1 f + 1 f +2.5 v sdin1 9 1 f 0.1 f + + 20 21 filt+ cmout 7 6 lrck sclk sdin3 sdin2 39 40 0.1 f 47 f va 0.1 f + 1 f 0.1 f +1.8 v to +5 v +5 v 4 43 13 analog conditioning and muting aouta1- aoutb1+ 38 37 analog conditioning and muting aoutb1- aouta2+ 35 36 analog conditioning and muting aouta2- aoutb2+ 34 33 analog conditioning and muting aoutb2- aouta3+ 29 30 analog conditioning and muting aouta3- aoutb3+ 28 27 analog conditioning and muting aoutb3- mutec1 41 26 mute drive mutec2 11 micro- controller vlc 0.1 f +1.8 v to +5 v 18 2 48 dsdb2 3 42 dsd_sclk dsda1 dsdb3 dsda3 dsdb1 dsda2 46 47 1 16 15 scl/cclk sda/cdin ado/cs rst 19 17 2 k 2 k note*: necessary for i 2 c control port operation note* mutec3 25 24 mutec4 mutec5 23 22 mutec6 cs4365 31 gnd gnd 5 tst 10, 12, 14, 44, 45 dsd audio source 220 470 470 digital audio source pcm figure 6. typical connection diagram, software mode
20 ds670f1 cs4365 vls cs4365 mclk vd aouta1+ 8 32 0.1 f + 1 f +2.5 v sdin1 9 1 f 0.1 f + + 20 21 filt+ cmout 7 6 lrck sclk sdin3 sdin2 39 40 0.1 f 47 f va 0.1 f + 1 f 0.1 f +1.8 v to +5 v +5 v 4 43 13 aouta1- aoutb1+ 38 37 aoutb1- aouta2+ 35 36 aouta2- aoutb2+ 34 33 aoutb2- aouta3+ 29 30 aouta3- aoutb3+ 28 27 analog conditioning and muting aoutb3- 11 31 gnd gnd 5 vlc 0.1 f +1.8 v to +5 v 18 2 48 dsdb2 3 12 m3 dsda1 dsdb3 dsda3 dsdb1 dsda2 46 47 1 16 15 m2 m1 m0 rst 19 17 22 mutec6 analog conditioning and muting 23 mutec5 analog conditioning and muting 24 mutec4 analog conditioning and muting 25 mutec3 analog conditioning and muting 26 mutec2 analog conditioning and muting 41 mutec1 stand-alone mode configuration dsd_sclk 42 10 m4 tst 14, 44, 45 dsd digital audio source pcm audio source 220 470 470 47 k optional figure 7. typical connection diagram, hardware mode
ds670f1 21 cs4365 4. applications the cs4365 serially accepts two?s complement formatted pcm data at standard audio sample rates including 48, 44.1 and 32 khz in ssm, 96, 88.2 and 64 khz in dsm, and 19 2, 176.4 and 128 khz in qsm. audio data is input via the serial data input pins (sdinx). the left/right clock (lrck) determines which channel is currently being input on sdinx, and the serial clock (sclk) clocks audio data in to the input data buffer. fo r more information on serial audio interfaces, see cirrus applicat ion note an282, ?the 2-channel se rial audio interface: a tutorial.? the cs4365 can be configured in hardware mode by the m0, m1, m2 , m3 and m4 pins and in software mode through i2c or spi. 4.1 master clock mclk/lrck must be an integer ratio as shown in tables 1 - 3 . the lrck frequency is equal to fs, the frequency at which words for each channel are input to the device. the mclk-to-lrck frequency ratio and speed mode is detected automatically during the init ialization sequence by counting the number of mclk transitions during a single lrck peri od and by detecting the absolute spe ed of mclk. internal dividers are then set to generate the proper internal clocks. tables 1 - 3 illustrate several standa rd audio sample rates and the required mclk and lrck frequencies. please note there is no required phase relationship, but mclk, lrck and sclk must be synchronous. sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x 1152x 32 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 table 1. single-speed mode standard frequencies sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 table 2. double-speed mode standard frequencies sample rate (khz) mclk (mhz) 64x 96x 128x 192x 256x 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 table 3. quad-speed mode standard frequencies = denotes clock ratio and sample rate combin ations which are not supported under auto speed-mode detection. please see ?switching characteristics - pcm? on page 15 .
22 ds670f1 cs4365 4.2 mode select in hardware mode, operation is determined by the mode select pins. the state of these pins are continually scanned for any changes. these pins require connec tion to supply or ground as outlined in figure 7 . for m0, m1, m2 supply is vlc and for m3 and m4 supply is vls. tables 4 - 6 show the decode of these pins. in software mode, the operational mode and data format are set in the fm and dif registers. see ?filter plots? on page 45 . m1 (dif1) m0 (dif0) description format figure 0 0 left-justified, up to 24-bit data 0 8 0 1 i2s, up to 24-bit data 1 9 1 0 right-justified, 16-bit data 2 10 1 1 right-justified, 24-bit data 3 11 table 4. pcm digital interface format, hardware mode options m4 m3 m2 (dem) description 0 0 0 single-speed without de-emphasis (4 to 50 khz sample rates) 0 0 1 single-speed with 44.1 khz de-emphasis; see figure 16 0 1 0 double-speed (50 to 100 khz sample rates) 0 1 1 quad-speed (100 to 200 khz sample rates) 1 0 0 auto speed-mode detect (32 khz to 200 khz sample rates) 1 0 1 auto speed-mode detect with 44.1 khz de-emphasis; see figure 16 1 1 x dsd processor mode (see table 6 for details) table 5. mode selection, hardware mode options m2 m1 m0 description 000 64x oversampled dsd data with a 4x mclk to dsd data rate 001 64x oversampled dsd data with a 6x mclk to dsd data rate 010 64x oversampled dsd data with a 8x mclk to dsd data rate 011 64x oversampled dsd data with a 12x mclk to dsd data rate 100 128x oversampled dsd data with a 2x mclk to dsd data rate 101 128x oversampled dsd data with a 3x mclk to dsd data rate 110 128x oversampled dsd data with a 4x mclk to dsd data rate 111 128x oversampled dsd data with a 6x mclk to dsd data rate table 6. direct stream digital (dsd), hardware mode options
ds670f1 23 cs4365 4.3 digital interface formats the serial port operates as a slav e and supports the i2s, left-justified, right-justified, and one-line mode (olm) digital interface formats with varying bit depths from 16 to 32, as shown in figures 8 - 15 . data is clocked into the dac on the rising edge. olm configuration is only supported in software mode. lrck sclk left channel right channel sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb msb lsb figure 8. format 0 - left -justified up to 24-bit data lrck sclk left channel right channel sdinx +3 +2 +1 +5 +4 -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb msb lsb lsb figure 9. format 1 - i2s up to 24-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 6543210 987 15 14 13 12 11 10 32 clocks figure 10. format 2 - ri ght-justified 16-bit data lrck sclk left channel sdinx 6543210 7 23 22 21 20 19 18 6543210 7 23 22 21 20 19 18 32 clocks 0 right channel figure 11. format 3 - right-justified 24-bit data lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 figure 12. format 4 - right-justified 20-bit data
24 ds670f1 cs4365 4.3.1 olm #1 olm #1 serial audio interface format operates in single-, double-, or quad-speed mode and will slave to sclk at 128 fs. six channels of msb first 20-bi t pcm data are input on sdin1. 4.3.2 olm #2 olm #2 serial audio interface format operates in single-, double-, or quad-speed mode and will slave to sclk at 256 fs. six channels of msb first 24-bit pcm data are input on sdin1. 4.4 oversampling modes the cs4365 operates in one of three oversampling modes based on the input sample rate. mode selection is determined by the m4, m3 and m2 pins in hardware mode or the fm bits in software mode. single-speed mode supports input sample rates up to 50 khz and uses a 128x oversampling ratio. double-speed mode supports input sample rates up to 100 khz and uses an oversampling ratio of 64x. quad-speed mode sup- ports input sample rates up to 200 khz and uses an oversampling ratio of 32x. the auto-speed mode detect feature allows for the autom atic selection of speed mode based off of the in- coming sample rate. this allows the cs4365 to accept a wide range of sample rates with no external inter- vention necessary. the auto-speed mode detect feature is available in both hardware and software mode. lrck sclk left channel right channel sdinx 6543210 987 15 14 13 12 11 10 10 6543210 987 15 14 13 12 11 10 17 16 17 16 32 clocks figure 13. format 5 - right-justified 18-bit data lrck sclk lsb msb 20 clks 64 clks 64 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac_a1 20 clks 20 clks 20 clks 20 clks 20 clks left channel right channel sdin1 dac_a2 dac_a3 dac_b1 dac_b2 dac_b3 figure 14. format 8 - one-line mode 1 lsb msb 24 clks 128 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb dac_a1 24 clks 24 clks 24 clks 24 clks 24 clks left channel right channel 128 clks lrck sclk sdin1 dac_a2 dac_a3 dac_b1 dac_b2 dac_b3 figure 15. format 9 - one-line mode 2
ds670f1 25 cs4365 4.5 interpolation filter to accommodate the increasingly complex requirements of digital audio systems, the cs4365 incorporates selectable interpolation filters for each mode of operatio n. a ?fast? and a ?slow? ro ll-off filter is available in each of single, double, and quad-speed modes. these filters have been designed to accommodate a va- riety of musical tastes and styles. the filt_sel bit is used to select which filter is used (see the ?filter plots? on page 45 for more details). when in hardware mode, only the ?f ast? roll-off filter is available. filter specifications can be found in section , and filter response plots can be found in figures 24 to 47 . 4.6 de-emphasis the cs4365 includes on-chip digital de-emphasis filt ers. the de-emphasis feature is included to accommo- date older audio recordings that utilize pre-emphasis equalizatio n as a means of noise reduction. figure 16 shows the de-emphasis curve. the frequency response of the de-em phasis curve will scale proportionally with changes in sample rate, fs if the input sample rate does not match the coefficient which has been se- lected. in software mode the required de-emphasis filter coef ficients for 32 khz, 44.1 khz, or 48 khz are selected via the de-emphasis control bits. in hardware mode only the 44.1 khz coefficient is available (enabled through the m2 pin). if the input sam- ple rate is not 44.1 khz and de-emphasis has been selected then the corner frequencies of the de-emphasis filter will be scaled by a factor of the actual fs over 44,100. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 16. de-emphasis curve
26 ds670f1 cs4365 4.7 atapi specification the cs4365 implements the channel-mixing functi ons of the atapi cd-rom specification. the atapi functions are applied per a-b pair. refer to table 9 on page 42 and figure 17 for additional informa- tion. 4.8 direct stream di gital (dsd) mode in software mode, the dsd/pcm bits (reg. 02h) are used to configure the device for dsd mode. the dsd_dif bits (reg 04h) then control the expected dsd rate and mclk ratio. the dir_dsd bit (reg 04h) selects between two pr oprietary methods for dsd-to-analog conversion. the first method uses a decimation-free dsd processing technique which allows for features such as matched pcm-level output, dsd volume control, and 50khz on -chip filter. the second method sends the dsd data directly to the on-chip switched-capacitor filter for conversion (without the above-mentioned features). the dsd_pm_en bit (reg. 04h) selects phase modulation (data plus data inverted) as the style of data input. in this mode, the dsd_pm_mode bit selects whet her a 128fs or 64x clock is used for phase modu- lated 64x data (see figure 18 ). use of phase modulation mode may not directly affect the performance of the cs4365, but may lower the sensitivity to board-level routing of the dsd data signals. the cs4365 can detect errors in the dsd data whic h does not comply with th e sacd specification. the static_dsd and invalid_dsd bits (reg. 04h) allow t he cs4365 to alter the incoming invalid dsd data. depending on the error, the data may either be attenuated or replaced with a muted dsd signal (the mutec pins would be set according to the damute bit (reg. 08h)). more information for any of thes e register bits can be found in section 7. ?filter plots? on page 45 . the dsd input structure and analog outputs are desi gned to handle a nominal 0 db-sacd (50% modulation index) at full rated performance. signals of +3 db-sac d may be applied for brief periods of time, however; performance at these levels is not guaranteed. if sustained +3 db-sacd levels are required, the digital vol- ume control should be set to -3.0 db. this same volume control register affects pcm output levels. there is no need to change the volume control setting between pcm and dsd in order to have the 0db output levels match (both 0 dbfs and 0 db-sacd will output at -3 db in this case). ? a channel volume control aout ax aoutbx left chan nel audio d ata right chan nel audio d ata bchannel volume control mute mute sdinx figure 17. atapi block diagram (x = channel pair 1, 2, or 3)
ds670f1 27 cs4365 4.9 grounding and power supply arrangements as with any high-resolution converter, the cs4365 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. the typical connec tion diagram shows the rec- ommended power arrangements, with va, vd, vlc, an d vls connected to clean supplies. if the ground planes are split between digital ground and analog gr ound, the gnd pins of th e cs4365 should be connect- ed to the analog ground plane. all signals, especially clocks, should be kept away from the filt+ and vq pins in order to avoid unwanted coupling into the dac. 4.9.1 capacitor placement decoupling capacitors should be placed as close to the dac as possible, with the low value ceramic ca- pacitor being the closest. to further minimize imped ance, these capacitors should be located on the same layer as the dac. if desired, all su pply pins with similar voltage ra tings may be connected to the same supply, but a decoupling capa citor should still be placed on each supply pin. notes: all decoupling capacitors should be referenced to ground. the cdb4365 evaluation board demonstrates the op timum layout and power supply arrangements. bcka (128fs) bckd (64fs) dsd_sclk dsdax, dsdbx d1 d1 d1 d0 d2 d2 d0 dsd_sclk dsdax, dsdbx bcka (64fs) dsd_sclk dsd phase modulation mode dsd normal mode not used not used not used figure 18. dsd phase modulation mode diagram
28 ds670f1 cs4365 4.10 analog output and filtering the application note ?design notes for a 2-pole filter with differential input? discusses the second-order butterworth filter and differential to single-ended co nverter which was implemented on the cs4365 evalua- tion board, cdb4365, as seen in figure 20 . the cs4365 does not include phase or amplitude compensa- tion for an external filter. ther efore, the dac system phase and am plitude response will be dependent on the external analog circuitry. the off-chip filter ha s been designed to attenuate the typical full-scale output level to below 2 vrms. figure 19 shows how the full-scale differential anal og output level specification is derived. aout+ aout- full-scale output level= (aout+) - (aout-)= 6.6 vpp 4.15 v 2.5 v 0.85 v 4.15 v 2.5 v 0.85 v figure 19. full-scale output figure 20. recommended output filter
ds670f1 29 cs4365 4.11 the mutec outputs the mutec1-6 pins have an auto-pola rity detect feature. the mutec output pins are high impedance at the time of reset. the external mute circuitry needs to be self-biased into an active state in order to be muted during reset. upon release of reset, the cs4365 will detect the status of the mu tec pins (high or low) and will then select that state as the polarity to driv e when the mutes become acti ve. the external-bias voltage level that the mutec pins see at the time of rele ase of reset must meet the ?mutec auto-detect input high/low voltage? specifications as outli ned in the digital characteristics section. figure 21 shows a single example of both an active high and an active low mute drive circuit. in these de- signs, the pull-up and pull-down resistors have been es pecially chosen to meet the input high/low threshold when used with the mmun2111 and mmun2211 internal bias resistances of 10 k . use of the mute control function is not mandatory, but re commended, for designs requiring the absolute minimum in extraneous clicks and pops. also, use of the mute control functi on can enable the system desi gner to achieve idle chan- nel noise/signal-to-noise rati os which are only limited by the external mute circuit. 4.12 recommended power-up sequence 4.12.1 hardware mode 1. hold rst low until the power supplies and configuration pi ns are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.1 . in this state, the registers are reset to the default settings, filt+ will remain low, an d vq will be connected to va/2. if rst can not be held low long enough the sdinx pins should remain static lo w until all other clocks are stable, and if possible the rst should be toggled low again once the system is stable. 2. bring rst high. the device will remain in a low power state with fi lt+ low and will initiate the hardware power-up sequence after approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad-speed mode). figure 21. recommended mute circuitry
30 ds670f1 cs4365 4.12.2 software mode 1. hold rst low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.1 . in this state, the registers are reset to the default settings, filt+ will remain low, and vq will be connected to va/2. 2. bring rst high. the device will remain in a low power state with filt + low for 512 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad- speed mode). 3. in order to reduce the chances of clicks and pops, perform a write to the cp_en bit prior to the completion of approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double- speed mode, and 2048 lrck cycles in quad-speed mode). the desired register settings can be loaded while keeping the pdn bit set to 1. set the rmp_up and rmp_dn bits to 1; then set the format and mode control bits to the desired settings. if more than the stated range of lrck cycles passes before cp en bit is written, the chip will enter hardware mode and begin to operate with the m0-m 4 as the mode settings. cpen bit may be written at anytime, even after the hardware sequence has begu n. it is advised that if the cpen bit cannot be set in time, the sdinx pins sh ould remain static low (this way no audio data can be converted incorrectly by the ha rdware mode settings). 4. set the pdn bit to 0. this will initiate the power-up se quence, which lasts approximately 50 s. 4.13 recommended procedure for switching operational modes for systems where the absolute minimum in clicks and pops is required, it is recommended that the mute bits are set prior to changing significant dac functions (such as changing sample rates or clock sources). the mute bits may then be released after clocks have settled and the proper modes have been set. it is required to have the device he ld in reset if the minimum high/low time specs of mclk cannot be met during clock source changes. 4.14 control port interface the control port is used to load all the internal regist er settings in order to operate in software mode (see section 7. ?filter plots? on page 45 ). the operation of the control port may be completely asynchronous with the audio sample rate. however, to avoid potential interference pr oblems, the control port pins should re- main static if no ope ration is required. the control port operates in one of two modes: i2c or spi. 4.14.1 map auto increment the device has map (memory addres s pointer) auto-increment capab ility enabled by the incr bit (also the msb) of the map. if incr is set to 0, map will stay constant for successive i2c writes or reads and spi writes. if incr is set to 1, m ap will auto-increment after each byte is written, allowing block reads or writes of successive registers. 4.14.2 i2c mode in the i2c mode, data is clocked into and out of the bi -directional serial control data line, sda, by the serial control port clock, scl (see figure 22 for the clock to data relationship). there is no cs pin. the ad0 pin enables the user to alter the chip address (001100[ad0][r/w ]) and should be tied to vlc or gnd, as re- quired, before powering up the device. if the device ever detects a high-to-low transition on the ad0/cs pin after power- up, spi mode will be selected.
ds670f1 31 cs4365 4.14.2.1 i2c write? to write to the device, follow the procedure below wh ile adhering to the control port switching specifica- tions in section . 1. initiate a start condition to the i2c bus followed by the address byte. the upper 6 bits must be 001100. the seventh bit must match the setting of the ad0 pin, and th e eighth must be 0. the eighth bit of the address byte is the r/w bit. 2. wait for an acknowledge (ack) from the part, then write to the memory address pointer, map. this byte points to the regi ster to be written. 3. wait for an acknowledge (ack) from the part, then write the desired data to the register pointed to by the map. 4. if the incr bit (see section 4.14.1 ) is set to 1, repeat the previous step until all the desired registers are written, then initiate a stop condition to the bus. 5. if the incr bit is set to 0 and furthe r i2c writes to other registers are desired, it is necessary to initiate a repeated start condition and follow the procedure detailed from step 1. if no further writes to other registers are desired, initiate a stop condition to the bus. 4.14.2.2 i2c read to read from the device, follow the procedure below while adhering to the cont rol port switching specifi- cations. 1. initiate a start condition to the i2c bus followed by the address byte. the upper 6 bits must be 001100. the seventh bit must match the setting of the ad0 pin, and th e eighth must be 1. the eighth bit of the address byte is the r/w bit. 2. after transmitting an acknowledge (ack), the devic e will then transmit the co ntents of the register pointed to by the map. the map register will contai n the address of the last register written to the map, or the default address (see section 4.14.1 ) if an i2c read is the first operation performed on the device. 3. once the device has transmitted th e contents of the register pointed to by the map, issue an ack. 4. if the incr bit is set to 1, the device will continue to transmit the contents of successive registers. con- tinue providing a clock and issue an ack after each byte until all the desired registers are read, then initiate a stop condition to the bus. 5. if the incr bit is set to 0 and further i2c reads from other re gisters are desired, it is necessary to initiate a repeated start condition and follow the procedure detailed from steps 1 and 2 from the i2c write instructions followed by step 1 of the i2c read sect ion. if no further reads from other registers are de- sired, initiate a stop condition to the bus. sda scl 001100 addr ad0 r/w start ack data 1-8 ack data 1-8 ack stop note: if operation is a write, this byte contains the memory address pointer, map. note 1 figure 22. control port timing, i2c mode
32 ds670f1 cs4365 4.14.3 spi ? mode in spi mode, data is clocke d into the serial control data line, cdin, by the serial control port clock, cclk (see figure 23 for the clock to data relationship). there is no ad0 pin. pin cs is the chip select signal and is used to control spi writes to the control port. wh en the device detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. all signals are inputs and data is clocked in on the rising edge of cclk. 4.14.3.1 spi write to write to the device, follow the procedure below wh ile adhering to th e control port switching specifica- tions in section . 1. bring cs low. 2. the address byte on the cdin pin must then be 00110000. 3. write to the memory address pointer, map. th is byte points to the register to be written. 4. write the desired data to the register pointed to by the map. 5. if the incr bit (see section 4.14.1 ) is set to 1, repeat the previous step until all the desired registers are written, then bring cs high. 6. if the incr bit is set to 0 and further spi writes to other registers are desired, it is necessary to bring cs high, and follow the procedure detailed from step 1. if no further writes to other registers are de- sired, bring cs high. 4.15 memory address po inter (map) map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 0011000 figure 23. control port timing, spi mode 4.15.1 incr (auto map increment enable) default = ?0? 0 - disabled 1 - enabled 4.15.2 map4-0 (memory address pointer) default = ?00000? 76543210 incr reserved reserved map4 map3 map2 map1 map0 00000000
ds670f1 33 cs4365 5. register quic k reference addr function 7 6 5 4 3 2 1 0 01h chip revision part4 part3 part2 part1 part0 rev rev rev default 0 1 1 0 1 x x x 02h mode control cpen freeze dsd/pcm reserved dac3_dis dac2_dis dac1_dis pdn default 0 0 0 0 0 0 0 1 03h pcm control dif3 dif2 dif1 dif0 reserved reserved fm1 fm0 default 0 0 0 0 0 0 1 1 04h dsd control dsd_dif2 dsd_dif1 dsd_dif0 dir_dsd static_d sd invalid_d sd dsd_pm_ md dsd_pm_ en default 0 0 0 0 1 0 0 0 05h filter control reserved reserved reserved r eserved reserved reserved reserved filt_sel default 0 0 0 0 0 0 0 0 06h invert control reserved reserved inv_b3 inv_a3 inv_b2 inv_a2 inv_b1 inv_a1 default 0 0 0 0 0 0 0 0 07h group control mutec1 mutec0 reserved p1_a=b p2_a=b p3_a=b reserved snglvol default 0 0 0 0 0 0 0 0 08h ramp and mute szc1 szc0 rmp_up rmp_dn pamute damute mute_p1 mute_p0 default 1 0 1 1 1 1 0 0 09h mute control reserved reserved mute_b3 mute_a3 mute_b2 mute_a2 mute_b1 mute_a1 default 0 0 0 0 0 0 0 0 0ah mixing control pair 1 (aoutx1) reserved p1_dem1 p1_dem0 p1atapi4 p1atapi3 p1atapi2 p1atapi1 p1atapi0 default 0 0 0 0 1 0 0 1 0bh vol. control a1 a1_vol7 a1_vol6 a1_vol5 a1_vol4 a1_vol3 a1_vol2 a1_vol1 a1_vol0 default 0 0 0 0 0 0 0 0 0ch vol. control b1 b1_vol7 b1_vol6 b1_vol5 b1_vol4 b1_vol3 b1_vol2 b1_vol1 b1_vol0 default 0 0 0 0 0 0 0 0 0dh mixing control pair 2 (aoutx1) reserved p2_dem1 p2_dem0 p2atapi4 p2atapi3 p2atapi2 p2atapi1 p2atapi0 default 0 0 0 0 1 0 0 1 0eh vol. control a2 a2_vol7 a2_vol6 a2_vol5 a2_vol4 a2_vol3 a2_vol2 a2_vol1 a2_vol0 default 0 0 0 0 0 0 0 0 0fh vol. control b2 b2_vol7 b2_vol6 b2_vol5 b2_vol4 b2_vol3 b2_vol2 b2_vol1 b2_vol0 default 0 0 0 0 0 0 0 0 10h mixing control pair 3 (aoutx1) reserved p3_dem1 p3_dem0 p3atapi4 p3atapi3 p3atapi2 p3atapi1 p3atapi0 default 0 0 0 0 1 0 0 1 11h vol. control a3 a3_vol7 a3_vol6 a3_vol5 a3_vol4 a3_vol3 a3_vol2 a3_vol1 a3_vol0 default 0 0 0 0 0 0 0 0 12h vol. control b3 b3_vol7 b3_vol6 b3_vol5 b3_vol4 b3_vol3 b3_vol2 b3_vol1 b3_vol0 default 0 0 0 0 0 0 0 0 16h pcm clock mode reserved reserved mclkdiv r eserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0
34 ds670f1 cs4365 6. register description note: all registers are read/write in i2c mode and write only in spi, unless otherwise noted. 6.1 chip revision (address 01h) 6.1.1 part number id (part) [read only] 01101- cs4365 revision id (rev) [read only] 000 - revision a0 001 - revision b0 function: this read-only register can be used to identi fy the model and revisi on number of the device. 6.2 mode control 1 (address 02h) 6.2.1 control port enable (cpen) default = 0 0 - disabled 1 - enabled function: this bit defaults to 0, allowing the device to power-up in stand-alone mode. the control port mode can be accessed by setting this bit to 1. this will allow the operation of the device to be controlled by the reg- isters, and the pin definitions will co nform to cont rol port mode. to accomplis h a clean power-up, the user should write this bit within 10 ms following the release of reset. 6.2.2 freeze controls (freeze) default = 0 0 - disabled 1 - enabled function: this function allows modifications to be made to th e registers without the changes taking effect until the freeze is disabled. to make multiple changes in the control port registers take effect simultaneously, enable the freeze bit, make all register changes, then disable the freeze bit. 76543210 part4 part3 part2 part1 part0 rev2 rev1 rev0 01100 - - - 76543210 cpen freeze dsd/pcm reserved dac3_dis dac2_dis dac1_dis pdn 00000001
ds670f1 35 cs4365 6.2.3 pcm/dsd selection (dsd/pcm ) default = 0 0 - pcm 1 - dsd function: this function selects dsd or pcm mode. the app ropriate data and clocks should be present before changing modes, or else mute should be selected. 6.2.4 dac pair disable (dacx_dis) default = 0 0 - enabled 1 - disabled function: when enabled, the respective dac channel pair x (aoutax and aoutbx) will rema in in a rese t state. it is advised that changes to these bits be made while the power-down bit is enabled to eliminate the pos- sibility of audible artifacts. 6.2.5 power down (pdn) default = 1 0 - disabled 1 - enabled function: the entire device will enter a lo w-power state when this fu nction is enabled, and the contents of the control registers are retained in this mode. the power-down bit defaults to ?enabled? on power-up and must be disabled before normal operation in control port mode can occur. 6.3 pcm control (address 03h) 6.3.1 digital interface format (dif) default = 0000 - format 0 (left-justified, up to 24-bit data) function: these bits select the interface format for the serial audio input. the dsd/pcm bit determines whether pcm or dsd mode is selected. the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format and the options are detailed in figures 8 through through 17 . 76543210 dif3 dif2 dif1 dif0 reserved reserved fm1 fm0 00000011
36 ds670f1 cs4365 6.3.2 functional mode (fm) default = 11 00 - single-speed mode (4 to 50 khz sample rates) 01 - double-speed mode (50 to 100 khz sample rates) 10 - quad-speed mode (100 to 200 khz sample rates) 11 - auto speed mode detect (3 2 khz to 200 khz sample rates) function: selects the required range of input sample rates or auto speed mode. 6.4 dsd control (address 04h) 6.4.1 dsd mode digital interface format (dsd_dif) default = 000 - format 0 (64x oversampled dsd data with a 4x mclk to dsd data rate) function: the relationship between the oversampling ratio of th e dsd audio data and the required master clock-to- dsd-data rate is defined by the digital interface format pins. the dsd/pcm bit determines whether pcm or dsd mode is selected. dif3 dif2 dif1 dif0 description format 0 0 0 0 left-justified, up to 24-bit data 0 0 0 0 1 i2s, up to 24-bit data 1 0 0 1 0 right-justified, 16-bit data 2 0 0 1 1 right-justified, 24-bit data 3 0 1 0 0 right-justified, 20-bit data 4 0 1 0 1 right-justified, 18-bit data 5 1000 one-line mode 1, 24-bit data 8 1001 one-line mode 2, 20-bit data 9 1010 reserved 1011 reserved x x x x all other combinations are reserved table 7. digital interface formats - pcm mode 765 4 3 2 1 0 dsd_dif2 dsd_dif1 dsd_dif0 dir_dsd stati c_dsd invalid_dsd dsd_pm_md dsd_pm_en 000 0 1 1 0 0 dif2 dif1 difo description 0 0 0 64x oversampled dsd data with a 4x mclk to dsd data rate 0 0 1 64x oversampled dsd data with a 6x mclk to dsd data rate 0 1 0 64x oversampled dsd data with a 8x mclk to dsd data rate 0 1 1 64x oversampled dsd data with a 12x mclk to dsd data rate 1 0 0 128x oversampled dsd data with a 2x mclk to dsd data rate 1 0 1 128x oversampled dsd data with a 3x mclk to dsd data rate 1 1 0 128x oversampled dsd data with a 4x mclk to dsd data rate 1 1 1 128x oversampled dsd data with a 6x mclk to dsd data rate table 8. digital interface formats - dsd mode
ds670f1 37 cs4365 6.4.2 direct dsd c onversion (dir_dsd) function: when set to 0 (default), dsd input data is sent to the dsd processor for filterin g and volume control func- tions. when set to 1, dsd input data is sent directly to the switched capacitor dacs for a pure dsd conversion. in this mode, the full-sc ale dsd and pcm levels will not be matched (see section ), the dynamic range performance may be reduced, the volume control is inac tive, and the 50 khz low pass filter is not available (see section for filter specifications). 6.4.3 static dsd detect (static_dsd) function: when set to 1 (default), the dsd processor checks fo r 28 consecutive zeroes or ones and, if detected, sends a mute signal to the dacs. the mutec pins will eventually go active according to the damute register. when set to 0, this function is disabled. 6.4.4 invalid dsd detect (invalid_dsd) function: when set to 1, the dsd processor checks for greater t han 24 out of 28 bits of the same value and, if de- tected, will attenu ate the data sent to the dacs. the mutec pins go active according to the damute register. when set to 0 (default), this function is disabled. 6.4.5 dsd phase modulation mo de select (dsd_pm_mode) function: when set to 0 (default), the 128fs (bcka) clock should be input to dsd_sclk for phase modulation mode. (see figure 18 on page 27 ) when set to 1, the 64fs (bckd) clock should be input to dsd_sclk for phase modulation mode. 6.4.6 dsd phase modulation mode enable (dsd_pm_en) function: when set to 1, dsd phase modulation input mode is enabled, and the dsd_pm_mode bit should be set accordingly. when set to 0 (default), this function is disabled (dsd normal mode).
38 ds670f1 cs4365 6.5 filter control (address 05h) 6.5.1 interpolation filt er select (filt_sel) function: when set to 0 (default), the interpolation filter has a fast roll-off. when set to 1, the interpolation filter has a slow roll-off. the specifications for each filter can be found in th e analog characteristics table, and response plots can be found in figures 24 to 47 . 6.6 invert control (address 06h) 6.6.1 invert signal polarity (inv_xx) function: when set to 1, this bit inverts the signal polarity of channel xx. when set to 0 (default), this function is disabled. 6.7 group control (address 07h) 6.7.1 mute pin control (mutec1, mutec0) default = 00 00 - six mute control signals 01, 10 - one mute control signal 11 - three mute control signals function: selects how the internal mute control signals are routed to the mutec1 through mutec6 pins. when set to ?00?, there is one mute control signal for each channel: aout1a on mutec1, aout1b on mutec2, etc. when set to ?01? or ?10?, there is a single mute control signal on the mutec1 pin. when set to ?11?, there are three mute control signals, one for each stereo pair: aout1a and aout1b on mutec1, aout2a and aout2b on mutec2, and aout3a and aout3b on mutec3. 76543210 reserved reserved reserved reserved reserved reserved reserved filt_sel 00000000 76543210 reserved reserved inv_b3 inv_ a3 inv_b2 inv_a2 inv_b1 inv_a1 00000000 76543210 mutec1 mutec0 reserved p1_a=b p2_a=b p3_a=b reserved snglvol 00000000
ds670f1 39 cs4365 6.7.2 channel a volume = ch annel b volume (px_a=b) default = 0 0 - disabled 1 - enabled function: the aoutax and aoutbx volume levels are independ ently controlled by the a and the b channel vol- ume control bytes when this function is disabled. the volume on both aoutax and aoutbx are deter- mined by the a channel attenuation and volume control bytes (per a-b pair), and the b channel bytes are ignored when this function is enabled. 6.7.3 single volume control (snglvol) default = 0 0 - disabled 1 - enabled function: the individual channel volume levels are independent ly controlled by their re spective volume control bytes when this function is disabled. the volume on all channels is determined by the a1 channel vol- ume control byte, and the other volume control bytes are ignored when this function is enabled. 6.8 ramp and mute (address 08h) 6.8.1 soft ramp and zero cross control (szc) default = 10 00 - immediate change 01 - zero cross 10 - soft ramp 11 - soft ramp on zero crossings function: immediate change when immediate change is select ed, all level changes will take effect immediately in one step. zero cross zero cross enable dictates that si gnal-level changes, either by at tenuation changes or muting, will occur on a signal zero crossing to mini mize audible artifacts. the reques ted level change will occur after a tim- eout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. soft ramp soft ramp allows level changes, both muting and a ttenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. 76543210 szc1 szc0 rmp_up rmp_dn pamute damute mute_p1 mute_p0 10111100
40 ds670f1 cs4365 soft ramp on zero crossing soft ramp and zero cross enable dictates that signal-level cha nges, either by attenuation changes or muting, will occur in 1/8 db steps an d be implemented on a signal zero crossing. the 1/8 db level change will occur after a timeout period betwee n 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. 6.8.2 soft volume ramp-up after error (rmp_up) function: an un-mute will be performed after ex ecuting an lrck/mclk ratio chan ge or error, and after changing the functional mode. when set to 1 (default), this unmute is effected, sim ilar to attenuation changes, by the soft and zero cross bits in the volume and mixing control register. when set to 0, an immediate unmut e is performed in these instances. note: for best results, it is recomme nded that this feature be used in conjunction with the rmp_dn bit. 6.8.3 soft ramp-down before fi lter mode change (rmp_dn) function: if either the filt_sel or dem bi ts are changed the dac will stop co nversion for a period of time to change its filter values. this bit selects how the data is effected prior to and af ter the change of the filter values. when set to 1 (default), a mute will be performed pr ior to executing a filter mode change an d an un-mute will be performed after executing the filter mode change. this mute a nd un-mute are effected, similar to attenuation changes, by the soft and zero cross bits in the volume and mixing control register. when set to 0, an immediate mute is performed prior to executing a filter mode change. note: for best results, it is recommended that this feature be used in conjunction with the rmp_up bit. 6.8.4 pcm auto-mute (pamute) function: when set to 1 (default), the digital-to-analog conv erter output will mute follo wing the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non-st atic data will release the mute. de- tection and muting is d one independently for each channel. the quiescent voltage on the output will be retained and the mute control pin will go active during the mute period. when set to 0, this function is disabled.
ds670f1 41 cs4365 6.8.5 dsd auto-mute (damute) function: when set to 1 (default), the digital -to-analog converter out put will mute following the reception of 256 re- peated 8-bit dsd mute patterns (as defined in the sacd specification). a single bit not fitting the repeated mu te pattern (mentioned above) will release the mute. detection and muting is done indepe ndently for each channel. the quiescent vo ltage on the output will be retained, and the mute control pin will go ac tive during the mute period. 6.8.6 mute polarity and detect (mutep1:0) default = 00 00 - auto polarity detect, selected from mutec1 pin 01 - reserved 10 - active low mute polarity 11 - active high mute polarity function: auto mute polarity detect (00) see section 4.11 ?the mutec outputs? on page 29 for description. active low mute polarity (10) when rst is low, the outputs are high impedance and will need to be bi ased active. once reset has been released and after this bit is set, the mutec output pins will be active low polarity. active high mute polarity (11) at reset time, the outputs are high impedance an d will need to be biased active. once reset has been released and after this bit is set, the mutec output pins will be active high polarity. 6.9 mute control (address 09h) 6.9.1 mute (mute_xx) default = 0 0 - disabled 1 - enabled function: the digital-to-analog converter out put will mute when enabled. the qu iescent voltage on the output will be retained. the muting function is affected, similarl y to attenuation changes, by the soft and zero cross bits. the mute pins will go ac tive during the mute period according to the mutec bits. 76543210 reserved reserved mute_b3 mute_a3 mute_b2 mute_a2 mute_b1 mute_a1 00000000
42 ds670f1 cs4365 6.10 mixing control (address 0ah, 0dh, 10h, 13h) 6.10.1 de-emphasis control (px_dem1:0) default = 00 00 - disabled 01 - 44.1 khz 10 - 48 khz 11 - 32 khz function: selects the appropriate digital filter to maintain the standard 15 s/50 s digital de-emphasis filter re- sponse at 32, 44.1 or 48 khz sample rates. (see figure 16 ) de-emphasis is only availa ble in single-speed mode. 6.11 atapi channel mixi ng and muting (atapi) default = 01001 - aoutax=al, aoutbx=br (stereo) function: the cs4365 implements the channel-mixing functi ons of the atapi cd-rom specification. the atapi functions are applied per a-b pair. refer to table 9 and figure 17 for additional information. 76543210 reserved px_dem1 px_dem0 pxatapi4 px atapi3 pxatapi2 pxatapi1 pxatapi0 00001001 atapi4 atapi3 atapi2 atapi1 atapi0 aoutax aoutbx 0 0 0 0 0 mute mute 00001 mute br 00010 mute bl 0 0 0 1 1 mute b[(l+r)/2] 00100 ar mute 00101 ar br 00110 ar bl 00111 ar b[(l+r)/2] 01000 al mute 01001 al br 01010 al bl 01011 al b[(l+r)/2] 0 1 1 0 0 a[(l+r)/2] mute 01101 a[(l+r)/2] br 01110 a[(l+r)/2] bl 0 1 1 1 1 a[(l+r)/2] b[(l+r)/2] 1 0 0 0 0 mute mute 10001 mute br 10010 mute bl table 9. atapi decode table
ds670f1 43 cs4365 6.12 volume control (address 0bh, 0ch, 0eh, 0fh, 11h, 12h) these six registers provide individual volume a nd mute control for each of the six channels. the values for ?xx? in the bit fields above are as follows: register address 0bh - xx = a1 register address 0ch - xx = b1 register address 0eh - xx = a2 register address 0fh - xx = b2 register address 11h - xx = a3 register address 12h - xx = b3 6.12.1 digital volume control (xx_vol7:0) default = 00h (0 db) function: the digital volume control registers allow independent control of the signal le vels in 1/2 db increments from 0 to -127.5 db. volume settings are decoded as shown in table 10 . the volume changes are imple- mented as dictated by the soft an d zero cross bits in the power and muting control register. note that the values in the volu me setting column in table 10 are approximate. the actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12. 1 0 0 1 1 mute [(bl+ar)/2] 10100 ar mute 10101 ar br 10110 ar bl 1 0 1 1 1 ar [(al+br)/2] 11000 al mute 11001 al br 11010 al bl 1 1 0 1 1 al [(al+br)/2] 1 1 1 0 0 [(al+br)/2] mute 1 1 1 0 1 [(al+br)/2] br 1 1 1 1 0 [(bl+ar)/2] bl 1 1 1 1 1 [(al+br)/2] [(al+br)/2] 76543210 xx_vol7 xx_vol6 xx_vol5 xx_vol4 xx_vol3 xx_vol2 xx_vol1 xx_vol0 00000000 binary code decimal value volume setting 00000000 0 0 db 00000001 1 -0.5 db 00000110 6 -3.0 db 11111111 255 -127.5 db table 10. example digital volume settings atapi4 atapi3 atapi2 atapi1 atapi0 aoutax aoutbx table 9. atapi decode table
44 ds670f1 cs4365 6.13 pcm clock mode (address 16h) 6.13.1 master clock divide by 2 enable (mclkdiv) function: when set to 1, the mclkdiv bit enables a circuit whic h divides the externally applied mclk signal by 2 prior to all other internal circuitry. when set to 0 (default), mclk is unchanged. 76543210 reserved reserved mclkdiv reserved reserved reserved reserved reserved 00000000
ds670f1 45 cs4365 7. filter plots 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 24. single-speed (fast) stopband rejectio n figure 25. single-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 26. single-speed (fast) transition band (detail) figure 27. single-speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 28. single-speed (slow) stopband rejection figure 29. sing le-speed (slow) transition band
46 ds670f1 cs4365 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) figure 30. single-speed (slow) transition band (d etail) figure 31. single-s peed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 32. double-speed (fast) stopband rejectio n figure 33. double-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 34. double-speed (fast) transition band (detail) figure 35. double-speed (fast) passband ripple
ds670f1 47 cs4365 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 36. double-speed (slow) stopband rejection figure 37. doub le-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.3 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 38. double-speed (slow) transition band (d etail) figure 39. double-speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 40. quad-speed (fast) stopband rejection figure 41. quad-speed (fast) transition band
48 ds670f1 cs4365 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.2 5 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 42. quad-speed (fast) transition band (detail) figure 43. quad-speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0. 9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 44. quad-speed (slow) stopband rejectio n figure 45. quad-speed (slow) transition band 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0. 9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.1 2 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 46. quad-speed (slow) transition band (det ail) figure 47. quad-speed (slow) passband ripple
ds670f1 49 cs4365 8. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral co mponents over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full-scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-n oise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measure- ment to full scale. this technique ensures that the distortion components are below the noise level and do not affect the measurement. this measurement te chnique has been accepted by the audio engineer- ing society, aes17-1991, and the electronic indu stries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right ch annels. measured for each channel at the converter's output with all zeros to the input under test and a fu ll-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain drift the change in gain value with temperature. units in ppm/c.
50 ds670f1 cs4365 9. package dimensions inches millimeters dim min nom max min nom max a --- 0.055 0.063 --- 1.40 1.60 a1 0.002 0.004 0.006 0.05 0.10 0.15 b 0.007 0.009 0.011 0.17 0.22 0.27 d 0.343 0.354 0.366 8.70 9.0 bsc 9.30 d1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e 0.343 0.354 0.366 8.70 9.0 bsc 9.30 e1 0.272 0.28 0.280 6.90 7.0 bsc 7.10 e* 0.016 0.020 0.024 0.40 0.50 bsc 0.60 l 0.018 0.24 0.030 0.45 0.60 0.75 0.000 4 7.000 0.00 4 7.00 * nominal pin pitch is 0.50 mm *controlling dimension is mm. *jedec designation: ms022 48l lqfp package drawing e1 e d1 d 1 e b l a1 a
ds670f1 51 cs4365 10.ordering information 11.references 1. how to achieve optimum performance fr om delta-sigma a/d & d/a converters , by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 2. cirrus logic datasheet cdb4365 av ailable at http ://www.cirrus.com 3. design notes for a 2-pole f ilter with diffe rential input , by steven green. cirrus logic application note an48 4. the i2c-bus specification: version 2.0 , philips semiconducto rs, december 1998. http://www.semicondu ctors.philips.com product description package pb-free grade temp range container order # cs4365 114 db, 192 khz 6- channel d/a converter 48-pin lqfp yes commercial -40 to +85 c tray cs4365-cqz tape & reel cs4365-cqzr automotive -40 to +105 c tray cs4365-dqz tape & reel CS4365-DQZR cdb4365 cs4365 evaluation board - - - - cdb4365
52 ds670f1 cs4365 12.revision history release changes pp3 updated guaranteed operati onal temperature range in ?recommended operating conditions? on page 8 . updated va, vlc, and vls cu rrent cunsumption specs updated fullscale output level updated dynamic perforamnce limits. removed voh specification updated vol specification f1 updated ?recommended operating conditions? on page 8 updated ?dac analog characteristics - commercial (-cqz)? on page 9 updated ?dac analog characteristics - automotive (-dqz)? on page 10 updated ?power and thermal characteristics? on page 11 updated legal information on page 52 contacting cirrus logic support for all product questions and inquiries, co ntact a cirrus logic sales representative. to find the one nearest to you, go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnis hing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semic onductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military applications, products surgical ly implanted into the body, au tomotive safety or security de- vices, life support products or other criti cal applications. inclusion of cirrus products in such applications is understood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantabi lity and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the custome r or customer?s customer uses or permits th e use of cirrus products in critical applica- tions, customer agrees, by such use, to fully indemnify cir rus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys? fees an d costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i2c is a registered trademark of philips semiconductor. spi is a trademark of motorola, inc.

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